New and emerging memory technologies, for example resistive change, or resistivity change, memory cells are gaining in popularity. Some examples include phase change (PCRAM) and conductive bridge (CB-RRAM) memories, all of which have limited endurance. For resistive change memories generally, the cumulative number of set or reset cycles the component memory cells may undergo before failure is finite and may be difficult to predict. Consequently, in typical applications, the host or memory/storage controller must either estimate or acquire a present endurance state of the constituent cells and actively manage and track their usage, striving to minimize the variance in usage of physical locations.
While erase count based estimates of durability or endurance may be adequate for NAND Flash wear leveling, this technique does not scale well for technologies like CB-RRAM or PCRAM, as the total amount of persistent storage required to maintain these counts increases with the smaller granularity of program/erase operations.
Improvements are needed to maximize the useful lives of memories.